TRUE-ARTDAC7 FPGA DEVELOPMENT BOARD MANUAL

1. Product Overview

The TRUE-ARTDAC7 FPGA Development Board is a domestically produced FPGA development platform designed for developing high-performance digital designs and embedded system applications. Developed based on the AMD Xilinx Artix-7 architecture, the board provides the fundamental infrastructure required for education, R&D, rapid prototyping, and hardware verification on a single platform.

Featuring a user-friendly structure, TRUE-ARTDAC7 allows for the development and testing of numerous FPGA-based applications without the need for additional hardware, thanks to its onboard peripheral hardware and user input/output units. The programming interfaces, memory structure, and expansion headers on the board offer a suitable environment for both entry-level applications and more advanced development studies.

The board features the XC7A50T-1FTG256C FPGA chip. Additionally, voltage levels of 1.0 V, 1.8 V, and 3.3 V are used within the system structure. Its compact dimensions of 14 cm × 8 cm provide a suitable mechanical infrastructure for desktop work, laboratory use, educational applications, and product demonstration processes.

1	JTAG Programming	11	Push Button
2	Programming Mode	12	2x40 DAC Pin Header
3	RX/TX LED	13	User LED
4	Reset Button	14	Buzzer
5	Done LED	15	RGB LED
6	UART/JTAG USB Port	16	User Switch
7	Power Mode	17	7-Segment
8	External Power Supply	18	2x40 DAC Pin Header
9	Power Switch	19	FPGA XC7A50T-1FTG256C
10	Power LED	20	FTDI FT2232HL-REEL

1	JTAG Programming	11	Push Button
2	Programming Mode	12	2x40 DAC Pin Header
3	RX/TX LED	13	User LED
4	Reset Button	14	Buzzer
5	Done LED	15	RGB LED
6	UART/JTAG USB Port	16	User Switch
7	Power Mode	17	7-Segment
8	External Power Supply	18	2x40 DAC Pin Header
9	Power Switch	19	FPGA XC7A50T-1FTG256C
10	Power LED	20	FTDI FT2232HL-REEL

2. FPGA CHIP

The TRUE-ARTDAC7 FPGA development board features the XC7A50T-1FTG256C FPGA chip from the AMD Xilinx Artix-7 family. This FPGA chip provides a suitable infrastructure for education, R&D, prototyping, and digital design applications, thanks to its architecture that combines low power consumption with high performance.

The XC7A50T model enables the realization of numerous FPGA-based applications with its logic resources, block RAM capacity, DSP units, and internal analog-to-digital converter structure. The FTG256 package preferred on the board provides sufficient input/output capacity for compact board designs while offering advantages in terms of board layout.

The Artix-7 FPGA chip used on the TRUE-ARTDAC7 board offers a suitable hardware infrastructure for the control of user input/output units, timing-based designs, communication applications, digital signal processing studies, and developments carried out with external modules.

Figure 2- 1: Features of the Utilized FPGA Family

Figure 2- 2: Chip Located on the Board

3. Power Architecture and Supply Structure

The TRUE-ARTDAC7 FPGA development board generates the necessary supply voltages for operation through the power regulation structure located on the board. The board's supply architecture is designed to provide the fundamental voltage levels required by the FPGA chip and peripheral units in a stable and secure manner.

There are three main supply lines on the board: 1.0 V, 1.8 V, and 3.3 V. These voltages are used respectively to power the FPGA core structure, auxiliary supply lines, and input/output peripheral units.

The power-on structure of the board is designed according to sequential activation logic. Upon the activation signal from the power switch, the 1.0 V regulator is first engaged. Subsequently, the 1.8 V regulator is activated using the Power Good (PG) output of this regulator. In the final stage, the 3.3 V supply line is generated. Thanks to this structure, the power rails are formed in a controlled sequence, ensuring a stable startup of the system.

The power converters used on the board are from the TPS56628DDAR series. Each regulator is configured to produce its respective voltage line.

Figure 3- 1: TRUE-ARTDAC7 Power Architecture Block Diagram

4. Configuration Modes

For the Artix-7 FPGA chip on the TRUE-ARTDAC7 FPGA development board to operate after power is applied, it must be programmed with a configuration file. This configuration data is a bitstream file that defines the logic functions and circuit connections to be implemented within the FPGA chip. This file, created in the Vivado design environment, can be uploaded to the board using different methods.

In JTAG configuration, the bitstream file is uploaded directly to the FPGA chip from a computer using the USB-JTAG interface. This method provides fast and practical use during the development and debugging processes. However, the configuration uploaded this way is temporary; when the power to the board is disconnected, the structure inside the FPGA is erased.

In QSPI Flash configuration, the bitstream file is written to the flash memory located on the board. When power is applied, the FPGA automatically starts by reading the data stored in this memory under the appropriate configuration settings. This method is suitable for permanent applications, demo projects, and scenarios requiring an automatic start at every power-on.

The configuration options and the related hardware structure for the TRUE-ARTDAC7 board are shown in the figure below.

Figure 4- 1: TRUE-ARTDAC7 Configuration Modes Connection Structure

5. Clock Source

The TRUE-ARTDAC7 FPGA development board features a 100 MHz oscillator as the system clock source. The oscillator model used on the board is the ASEM1-100.000MHZ-LC-T. This oscillator is integrated into the board to be used as the FPGA clock input for various designs.

Depending on the application being developed, different frequencies can be derived from this 100 MHz input clock by utilizing the clock management resources (CMTs) within the FPGA chip. This allows for the generation of various operating frequencies required by the specific design.

Figure 5- 1: TRUE-ARTDAC7 System Clock Block Diagram

Figure 5- 2: Oscillator Located on the Board

Tablo 5- 1: CLK Pin Ataması

CLK Pin Name	FPGA Pin Name	FPGA Pin
CLK100MHZ	IO_L13P_T2_MRCC_14	N11

6. QSPI Flash Memory

The TRUE-ARTDAC7 FPGA development board features a 128 Mbit QSPI Flash memory for system configuration and non-volatile data storage. The flash memory model used on the board is the Micron MT25QL128ABA1ESE-0SIT, which operates at a 3.3 V CMOS logic level.

Thanks to its non-volatile structure, the QSPI Flash memory can be used to store FPGA configuration data. With the appropriate mode settings, the FPGA can automatically read and boot from the bitstream file stored in this memory upon power-up. This architecture ensures that designs are not only temporarily loaded via JTAG but can also be written to the flash memory so that the FPGA chip is programmed every time the board is energized.

The QSPI Flash memory is connected to dedicated pins on the FPGA chip reserved for configuration purposes. The hardware connection and related lines for the memory are shown in the schematic.

Figure 6- 1: TRUE-ARTDAC7 QSPI Flash Connection Structure

Figure 6- 2: TRUE-ARTDAC7 QSPI FLASH Schematic Connection

Table 6- 1: QSPI Flash Pin Assignment

QSPI Pin Name	FPGA Pin Name	FPGA Pin
FLASH_CS	IO_L6P_T0_FCS_B_14	L12
FLASH_CLK	CCLK_0	E8
FLASH_DQ0	IO_L1P_T0_D00_MOSI_14	J13
FLASH_DQ1	IO_L1N_T0_D01_DIN_14	J14
FLASH_DQ2	IO_L2P_T0_D02_14	K15
FLASH_DQ3	IO_L2N_T0_D03_14	K16

Figure 6- 3: QSPI FLASH Located on the Board

7. USB-JTAG / USB-UART Interface

The FT2232HL-REEL USB bridge integrated circuit is used on the TRUE-ARTDAC7 FPGA development board to perform programming and communication operations. Thanks to this structure, users can communicate with the board only via a USB connection without the need for an external programmer.

The FT2232HL-REEL integrated circuit fulfills two basic functions on the board. The first of these is the transport of JTAG programming and debugging signals of the FPGA chip. In this way, bitstream can be directly uploaded to the FPGA chip via development environments such as Vivado and hardware development processes are facilitated. The basic signals used in the JTAG interface are TCK, TMS, TDI and TDO lines.

The second function of the integrated circuit is to provide the USB-UART communication structure. In this way, serial communication can be performed between the computer and the FPGA chip. Data sent and received over the UART interface can be used in user applications with appropriate TX/RX connections within the design. This structure provides significant convenience in terms of data transmission, monitoring error messages and developing communication applications.

Although the USB-JTAG and USB-UART functions on the board are provided through the same integrated circuit, they operate independently of each other. Thus, the user can both perform FPGA programming operations and use UART communication over a single USB connection.
The hardware connection and related signal structure of the FT2232HL-REEL integrated circuit on the TRUE-ARTDAC7 board are shown on the schematic.

Figure 7- 1: TRUE-ARTDAC7 FT2232HL Connection Structure

Figure 7- 2: FTDI Located on the Board

Table 7- 1: JTAG/USB-UART Pin Assignment

FTDI Pin Name	FPGA Pin Name	FPGA Pin
TCK	TCK_0	L7
TMS	TMS_0	M7
TDI	TDI_0	N7
TDO	TDO_0	N8
UART_TXD_IN	IO_L6P_T0_35	D6
UART_RXD_OUT	IO_L6N_T0_VREF_35	D5

8. User Input/Output Units

The TRUE-ARTDAC7 FPGA development board is equipped with various user input/output units to enable the realization of basic digital design applications without the need for additional hardware. The board features 16 switches, 16 user LEDs, 5 push buttons, 1 RGB LED, 1 buzzer, and a 4-digit 7-segment display.

These peripheral units allow for the direct implementation of fundamental functions such as reading inputs, driving outputs, status indication, user interaction, audible alerts, and numerical data display within FPGA-based designs. Thus, users can quickly develop and test logic circuits, counter applications, stopwatches, state machines, PWM-based control structures, and various verification scenarios.

The connections between the user input/output units on the board and the FPGA chip are shown in the images below.

Figure 8- 1: Basic User Input/Output Connection Structure on the TRUE-ARTDAC7 Board

Table 8- 1: User Input-Output Units Pin Assignment Table

Signal Name	FPGA Pin Name	PIN assignment
SW1	IO_L7P_T1_34	R2
SW2	IO_L8P_T1_34	R3
SW3	IO_L9P_T1_DQS_34	T4
SW4	IO_L23N_T3_A02_D18_14	T5
SW5	IO_L19N_T3_A09_D25_VREF_14	N6
SW6	IO_L24P_T3_A01_D17_14	R6
SW7	IO_L21P_T3_DQS_14	T7
SW8	IO_L21N_T3_DQS_A06_D22_14	T8
SW9	IO_L20P_T3_A08_D24_14	P8
SW10	IO_L18N_T2_A11_D27_14	P9
SW11	IO_L17P_T2_A14_D30_14	R10
SW12	IO_L18P_T2_A12_D28_14	N9
SW13	IO_L14N_T2_SRCC_14	P11
SW14	IO_L15N_T2_DQS_DOUT_CSO_B_14	T12
SW15	IO_L16N_T2_A15_D31_14	T13
SW16	IO_L10P_T1_D14_14	T14
LD1	IO_L8N_T1_34	T2
LD2	IO_L9N_T1_DQS_34	T3
LD3	IO_L23P_T3_A03_D19_14	R5
LD4	IO_L10P_T1_34	P5
LD5	IO_25_14	P6
LD6	IO_L19P_T3_A10_D26_14	M6
LD7	IO_L24N_T3_A00_D16_14	R7
LD8	IO_L20N_T3_A07_D23_14	R8
LD9	IO_L22P_T3_A05_D21_14	T9
LD10	IO_L14P_T2_SRCC_14	P10
LD11	IO_L22N_T3_A04_D20_14	T10
LD12	IO_L17N_T2_A13_D29_14	R11
LD13	IO_L15P_T2_DQS_RDWR_B_14	R12
LD14	IO_L16P_T2_CSI_B_14	R13
LD15	IO_L11N_T1_SRCC_14	P13
LD16	IO_L10N_T1_D15_14	T15
BTNL	IO_L9N_T1_DQS_D13_14	R16
BTNR	IO_L9P_T1_DQS_14	R15
BTNU	IO_L4N_T0_D05_14	M14
BTND	IO_L3N_T0_DQS_EMCCLK_14	M15
BTNC	IO_L7P_T1_D09_14	M16
LDR	IO_L7N_T1_D10_14	N16
LDG	IO_L8P_T1_D11_14	P15
LDB	IO_L8N_T1_D12_14	P16
Buzzer	IO_L11P_T1_SRCC_14	N13
AN0	IO_L6N_T0_VREF_34	N4
AN1	IO_L5P_T0_34	P4
AN2	IO_L1P_T0_34	L4
AN3	IO_0_34	L5
7SEG_A	IO_L4N_T0_34	P1
7SEG_B	IO_L3P_T0_DQS_34	N3
7SEG_C	IO_L1N_T0_34	M4
7SEG_D	IO_L3N_T0_DQS_34	N2
7SEG_E	IO_L4P_T0_34	N1
7SEG_F	IO_L7N_T1_34	R1
7SEG_G	IO_L6P_T0_34	M5
DP (dot)	IO_L5N_T0_34	P3

9. DAC Interface Headers and Expansion Structure

The TRUE-ARTDAC7 FPGA development board features two pin headers, designated as J1 and J2, for connecting external DAC modules and similar expansion boards. These headers provide direct access to the FPGA I/O lines, allowing users to integrate different modules and peripherals into the system.

The J1 and J2 headers are designed as 2x20, 2.54 mm dual-row connectors. Both headers include power and ground lines along with user input/output pins connected to the FPGA chip. This structure ensures that the board serves not only for basic education and testing but also as a flexible development platform compatible with DAC/ADC modules and special-purpose external boards.

The I/O lines on the DAC interface headers operate at a 3.3 V logic level. Additionally, a 5 V supply line (VU), 3.3 V supply lines, and GND pins are provided to the user on these headers. This configuration offers practical use for powering external modules and organizing signal connections efficiently.

The schematic connections and physical pin layouts for the J1 and J2 headers are shown in the figures below.

Figure 9- 2: TRUE-ARTDAC7 DAC Pin Header Pin Assignments

Figure 9- 1: TRUE-ARTDAC7 DAC Pin Header Schematic Connections

Table 9- 1: J1 Pin Assignment Table

J1 PIN	Signal Name	FPGA Pin Name	PIN Assignment
PIN1	GND	-	-
PIN2	+5V	-	-
PIN3	EX_IO_1N	IO_L2N_T0_34	M1
PIN4	EX_IO_1P	IO_L2P_T0_34	M2
PIN5	EX_IO_2N	IO_L23N_T3_35	L2
PIN6	EX_IO_2P	IO_L23P_T3_35	L3
PIN7	EX_IO_3N	O_L22N_T3_35	J1
PIN8	EX_IO_3P	O_L22P_T3_35	K1
PIN9	EX_IO_4N	IO_L24N_T3_35	K2
PIN10	EX_IO_4P	IO_L24P_T3_35	K3
PIN11	EX_IO_5N	IO_L21N_T3_DQS_35	H3
PIN12	EX_IO_5P	IO_L21P_T3_DQS_35	J3
PIN13	EX_IO_6N	IO_L20N_T3_35	H1
PIN14	EX_IO_6P	IO_L20P_T3_35	H2
PIN15	EX_IO_7N	IO_L18N_T2_35	H4
PIN16	EX_IO_7P	IO_L18P_T2_35	H5
PIN17	EX_IO_8N	IO_L16N_T2_35	G4
PIN18	EX_IO_8P	IO_L16P_T2_35	G5
PIN19	EX_IO_9N	IO_L17N_T2_35	G1
PIN20	EX_IO_9P	IO_L17P_T2_35	G2
PIN21	EX_IO_10N	IO_L15N_T2_DQS_35	E1
PIN22	EX_IO_10P	IO_L15P_T2_DQS_35	F2
PIN23	EX_IO_11N	IO_L11N_T1_SRCC_35	D3
PIN24	EX_IO_11P	IO_L11P_T1_SRCC_35	E3
PIN25	EX_IO_12N	IO_L10N_T1_AD15N_35	D1
PIN26	EX_IO_12P	IO_L10P_T1_AD15N_35	E2
PIN27	EX_IO_13N	IO_L9N_T1_DQS_AD7N_35	B1
PIN28	EX_IO_13P	IO_L9P_T1_DQS_AD7N_35	C1
PIN29	EX_IO_14N	IO_L8N_T1_AD14N_35	A2
PIN30	EX_IO_14P	IO_L8P_T1_AD14N_35	B2
PIN31	EX_IO_15N	IO_L4N_T0_35	A3
PIN32	EX_IO_15P	IO_L4P_T0_35	B4
PIN33	EX_IO_16N	IO_L3N_T0_DQS_AD5N_35	A4
PIN34	EX_IO_16P	IO_L3N_T0_DQS_AD5P_35	A5
PIN35	EX_IO_17N	IO_L1N_T0_AD4N_35	A7
PIN36	EX_IO_17P	IO_L1N_T0_AD4P_35	B7
PIN37	GND	-	-
PIN38	GND	-	-
PIN39	+3.3V	-	-
PIN40	+3.3V	-	-

Table 9- 2: J2 Pin Assignment Table

J1 PIN	Signal Name	FPGA Pin Name	PIN Assignment
PIN1	GND	-	-
PIN2	+5V	-	-
PIN3	EX_IO_18N	IO_L2N_T0_AD8N_15	A9
PIN4	EX_IO_18P	IO_L2N_T0_AD8P_15	A8
PIN5	EX_IO_19N	IO_L3P_T0_DQS_AD1P_15	B9
PIN6	EX_IO_19P	IO_L3P_T0_DQS_AD1N_15	A10
PIN7	EX_IO_20N	IO_L4N_T0_15	B11
PIN8	EX_IO_20P	IO_L4P_T0_15	B10
PIN9	EX_IO_21N	IO_L5P_T0_AD9N_15	A12
PIN10	EX_IO_21P	IO_L5P_T0_AD9P_15	B12
PIN11	EX_IO_22N	IO_L7N_T1_AD2N_15	A14
PIN12	EX_IO_22P	IO_L7N_T1_AD2P_15	A13
PIN13	EX_IO_23N	IO_L8N_T1_AD10N_15	C14
PIN14	EX_IO_23P	IO_L8N_T1_AD10P_15	B14
PIN15	EX_IO_24N	IO_L9N_T1_DQS_AD3N_15	A15
PIN16	EX_IO_24P	IO_L9N_T1_DQS_AD3P_15	H5
PIN17	EX_IO_25N	IO_L10N_T1_AD11N_15	B16
PIN18	EX_IO_25P	IO_L10N_T1_AD11P_15	C16
PIN19	EX_IO_26N	IO_L13N_T2_MRCC_15	E13
PIN20	EX_IO_26P	IO_L13P_T2_MRCC_15	E12
PIN21	EX_IO_27N	IO_L15N_T2_DQS_ADV_B_15	D15
PIN22	EX_IO_27P	IO_L15P_T2_DQS_ADV_B_15	D14
PIN23	EX_IO_28N	IO_L16N_T2_A27_15	F13
PIN24	EX_IO_28P	IO_L16P_T2_A27_15	F12
PIN25	EX_IO_29N	IO_L17N_T2_A25_15	D16
PIN26	EX_IO_29P	IO_L17P_T2_A25_15	E16
PIN27	EX_IO_30N	IO_L18N_T2_A23_15	E15
PIN28	EX_IO_30P	IO_L18P_T2_A23_15	F15
PIN29	EX_IO_31N	IO_L21N_T3_DQS_A18_15	F14
PIN30	EX_IO_31P	IO_L21P_T3_DQS_A18_15	G14
PIN31	EX_IO_32N	IO_L22N_T3_A16_15	G16
PIN32	EX_IO_32P	IO_L22P_T3_A16_15	H16
PIN33	EX_IO_33N	IO_L23N_T3_FWE_B_15	J16
PIN34	EX_IO_33P	IO_L23P_T3_FWE_B_15	J15
PIN35	EX_IO_34N	IO_L24N_T3_RS0_15	G15
PIN36	EX_IO_34P	IO_L24P_T3_RS0_15	H14
PIN37	GND	-	-
PIN38	GND	-	-
PIN39	+3.3V	-	-
PIN40	+3.3V	-	-

10. Building Diagram

Figure 10- 1: Dimensional Top View of the TRUE-ARTDAC7 Board